Intel promises one trillion transistors on package by 2030 -

Intel promises one trillion transistors on package by 2030 –

Intel Research Powers Moore’s Law, Paving the Way to One Trillion Transistors by 2030

At IEDM 2022, the 75th anniversary of the transistor, Intel is aiming for a further 10-fold improvement in density in packaging technology and using a new material just 3 atoms thick to advance the scale of the transistor.

What’s new: Today, Intel unveiled research breakthroughs fueling its innovation pipeline to keep Moore’s Law on track to reach one trillion transistors in one package over the next decade. At the IEEE International Electron Devices Meeting (IEDM) 2022, Intel researchers showcased advances in 3D packaging technology with a new 10x density improvement; new materials for scaling 2D transistors beyond RibbonFET, including ultra-thin material just 3 atoms thick; new possibilities in power and memory efficiency for more efficient computing; and advances in quantum computing.

“Seventy-five years after the invention of the transistor, the innovation behind Moore’s Law continues to meet the exponential increase in global demand for computing. At MEI 2022, Intel is showcasing both the cutting-edge and real-world research advancements needed to overcome current and future barriers, meet this insatiable demand, and keep Moore’s Law alive for years to come.

–Gary Patton, Intel Vice President and General Manager, Components Research and Design Enablement

What happens at the MEI: To commemorate the 75th anniversary of the transistor, Dr. Ann Kelleher, Intel’s Executive Vice President and General Manager of Technology Development, will host a plenary session at the MEI. Kelleher will outline pathways for continued industry innovation – rallying the ecosystem around a systems-based strategy to meet the growing global demand for computing and innovate more effectively to advance at the pace of the law of Moore. The session “Let’s celebrate 75 years of the transistor!” A Look at the Evolution of Moore’s Law Innovation,” takes place at 9:45 a.m. PST on Monday, December 5.

Why is this important: Moore’s Law is key to meeting the world’s insatiable computing needs, as rising data consumption and the trend towards increased artificial intelligence (AI) are driving the greatest acceleration in demand ever.

Continuous innovation is the cornerstone of Moore’s Law. Over the past two decades, many of the key innovation milestones for continuous power, performance, and cost improvements—including strained silicon, Hi-K metal gate, and FinFET—in computers personal, GPUs and data centers started with Intel’s Component Research Group. Other research, including RibbonFET gate-all-around (GAA) transistors, PowerVia back-feed technology, and packaging breakthroughs like EMIB and Foveros Direct, are on the roadmap today.

At IEDM 2022, Intel’s Component Research Group demonstrated its commitment to innovation in three key areas to pursue Moore’s Law: new 3D hybrid bonding packaging technology to enable seamless chip integration ; ultra-thin 2D materials to fit more transistors on a single chip; and new possibilities in power and memory efficiency for higher performance computing.

How we do it: Researchers in the Components Research Group have identified new materials and processes that blur the line between packaging and silicon. We reveal the critical next steps on the journey to extending Moore’s Law to one trillion transistors in one package, including an advanced package that can achieve 10x more interconnect density, leading to near-monolithic chips. Intel’s hardware innovations have also identified practical design choices that can meet the demands of scaling transistors using a new material just 3 atoms thick, allowing the company to continue to scale. beyond the RibbonFET.

Intel introduces near-monolithic chips for next-generation 3D packaging:

  • Intel’s latest Hybrid Link research presented at IEDM 2022 shows an additional 10x improvement in density for power and performance compared to Intel’s IEDM 2021 research presentation.
  • Continuous scaling of the hybrid link at 3um pitch allows for interconnect densities and bandwidths similar to those found on monolithic system-on-chip connections.

Intel turns to ultra-thin ‘2D’ materials to fit more transistors on a single chip:

  • Intel demonstrated an all-around-gate stacked nanosheet structure using a 2D channel material only 3 atoms thick, while achieving near-ideal switching of transistors on a dual-gate structure at room temperature with low current of leak. These are two key breakthroughs needed to stack GAA transistors and go beyond the fundamental limits of silicon.
  • The researchers also revealed the first comprehensive analysis of electrical contact topologies to 2D materials that could pave the way for high-performance and scalable transistor channels.

Intel offers new power and memory efficiency possibilities for higher performance computing:

  • To use chip area more efficiently, Intel is redefining scaling by developing memory that can be placed vertically above transistors. In an industry first, Intel is introducing stacked ferroelectric capacitors that match the performance of conventional ferroelectric trench capacitors and can be used to build FeRAM on a logic chip.
  • An industry-first device-level model captures mixed phases and faults for enhanced ferroelectric hafnia devices, marking significant progress for Intel in supporting industry tools to develop new new memories and ferroelectric transistors.
  • By bringing the world closer to transitioning beyond 5G and solving energy efficiency challenges, Intel is building a viable path to 300 millimeter GaN-on-silicon wafers. Intel’s breakthroughs in this area demonstrate 20 times greater gain than the industry standard GaN and set an industry record figure of merit for high performance power delivery.
  • Intel is making inroads into super power-efficient technologies, especially transistors that don’t forget, retaining data even when power is removed. Already, Intel researchers have broken down two of the three barriers preventing the technology from being fully viable and operational at room temperature.

Intel continues to introduce new concepts in physics with breakthroughs in delivering better qubits for quantum computing:

  • Intel researchers are working to find better ways to store quantum information by gathering a better understanding of various interface defects that could act as environmental disturbances affecting quantum data.

“end of press release”

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